You are here : Home > Projet SUPERAID-7

Europe


SUPERAID7

In the SUPERAID7 project, the variability induced by different sources of process variation has been investigated in relation to the performance of Gate-All-Around Stacked-Nanosheet MOSFET. After fabricating devices, the CEA-Leti-NSP model was developed, validated and calibrated using experimental data. Subsequently, the extracted variability-aware compact models demonstrated how different process parameters can affect different aspects of circuit behavior, which is a key issue for future advanced CMOS technology nodes.


Published on 23 April 2021

​

Stability Under Process Variability for Advanced Interconnects and Devices Beyond 7 nm node

In the SUPERAID7 project, the variability induced by different sources of process variation has been investigated in relation to the performance of Gate-All-Around Stacked-Nanosheet MOSFET. After fabricating devices, the CEA-Leti-NSP model was developed, validated and calibrated using experimental data. Subsequently, the extracted variability-aware compact models demonstrated how different process parameters can affect different aspects of circuit behavior, which is a key issue for future advanced CMOS technology nodes.





 

Starting date : Jan. 2016 > Dec. 2018

Lifetime: 36 months

Program in support : H2020-ICT-25-2015


 

Status project : complete


CEA-Leti's contact :

Sylvain Barraud

 

Project Coordinator: Fraunhofer IISB (DE)

Partners:  

  • TU Wien, (AT)
  • CEA-Leti, (FR)
  • Gold Standard Simulans (Synopsis), (UK)
  • University of Glasgow, (UK)


Publications:

  • «Electrical characterization of vertically stacked p-FET SOI nanowires», B. Cardoso Paz, M. Cassé, S. Barraud, G. Reimbold, M. Vinet, O. Faynot, M. Pavanello, Solid-State Electronics, 141, 84, 2018.
  • «Methodology to separate channel conductions of two level vertically stacked SOI nanowire MOSFETs», B. Cardoso Paz, M. Cassé, S. Barraud, G. Reimbold, M. Vinet, O. Faynot, M. Pavanello, Solid-State Electronics, 149, 62, 2018.
  • «Top-down fabrication and electrical characterization of Si and SiGe nanowires for advanced CMOS technologies», S. Barraud, B. Previtali, V. Lapras, R. Coquand, C. Vizioz, J.-M. Hartmann, M. Cassé, Submitted to Semiconductor Science and Technology.
  • «New method for individual electrical characterization of stacked SOI nanowire MOSFETs», B. Cardoso Paz, M. Cassé, S. Barraud, G. Reimbold, M. Vinet, O. Faynot, M. Pavanello, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2017: DOI: 10.1109/ S3S.2017.8309237.
  • «Performance and transport analysis of vertically stacked p-FET SOI nanowires», B. Cardoso Paz, M. Pavanello, M. Cassé, S. Barraud, G. Reimbold, M. Vinet, O. Faynot, EUROSOI-ULIS Workshop, 2017, DOI: 10.1109/ ULIS.2017.7962606.
  • «An improved mobility model for FDSOI TriGate and other Multi-Gate Nanowire MOSFETs down to nm-scale dimensions», M. Cassé, J. Pelloux-Prayer, Z. Zeng, Y.-M Niquet, F. Triozon, S. Barraud, G. Reimbold, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2017: DOI: 10.1109/S3S.2017.8309241.
  • «Stacked-Nanowires/Nanosheets GAA MOSFETs – From technology to design enablement «– Oral invited, S. Barraud & al., SSDM conference, Sendai, Japan, 2017.
  • «Performance and design considerations for Gate-All-Around Stacked-Nanowires FETs» – Oral invited, S. Barraud & al., IEDM conference, San-Francisco, US, 2017.
  • «Tunability of parasitic channel in GAA stacked nanosheets», S. Barraud & al., IEDM conference, San-Francisco, US, 2018.



​

Investment:  € 3.4 m.

EC Contribution: € 3.4 m.



Website


Stakes

  • CEA-Leti first described and summarized a very detailed database of morphological/electrical results from Trigate nanowire devices, including a wide range of NW widths (8 nm £ W £ 10 μm), NW heights (6 nm £ Hfin £ 24 μm) and transport orientations (along [110] and [100] direction). Electron and hole transport was described for both unstrained and (tensile/compressive) strained Si and SiGe channels.

  • CEA-Leti then designed and specified the Gate-All-Around (GAA) stacked nanowire devices including inner spacers and SiGe source-drain (S/D) stressors. The Precession Electron Diffraction (PED) method was applied for the first time at nm-scale accuracy. It was used to quantify deformation and provide useful information on strain fields at different fabrication stages. Two major challenges facing development of stacked wire technology were addressed, specifically inner spacers and strain engineering in 3D integration processes.

  • Finally, a comprehensive study ranging from integration of 3D Gate-All-Around stacked nanowire MOSFET devices to SPICE modeling was conducted. Devices were successfully fabricated on SOI substrates using a replacement high-K metal gate process and self-aligned contacts. Backbiasing
    was efficiently used to highlight a drastically improved electrostatics in the upper GAA Si channels. Advanced electrical characterization of these devices enabled CEA-Leti to calibrate a new version of the physical compact model (CEA-Leti-NSP) to assess the performance of GAA
    FET ring oscillators.

OBJECTIVES

  • Process variability is ever more critical among the physical limitations that curb progress in nanoelectronics for aggressively scaled More-than-Moore systems. The effects of different sources of process variation, both systematic and stochastic, influence each other and lead to variations in the electrical, thermal and mechanical behavior of devices, interconnects and circuits. Correlations are of prime importance because they drastically affect the percentage of products that meet specifications. Although comprehensive experimental investigation of these effects is largely impossible, modelling and simulation (TCAD) offers the unique possibility of predefining process variations and tracing their effects on subsequent process steps and on manufactured devices and circuits simply by changing the relevant input data. This major requirement for and capability of simulation are, among other needs, highlighted in the International Technology Roadmap for Semiconductors (ITRS).

  • SUPERAID7 builds upon the successful FP7 SUPERTHEME project, which focused on advanced More-than-Moore devices.
    It is aimed at establishing a software system for simulating the impact of systematic and statistical process variations on advanced More-than-Moore devices, circuits and especially interconnects down to the 7 nm node and below. This requires better physical models and extended compact models. Device architectures addressed in the benchmarks include TriGate/ΩGate FETs and stacked nanowires including alternative channel materials. The software developed can be benchmarked using CEA-Leti background and sideground experiments. Main areas of usage include software commercialization through partner Synopsis and support for device architecture activitities at CEA-Leti.




IMPACT

  • The project has been implemented, kept up-to-date and in use for internal and public information since March 2016. To date, 40 research papers have been published on the strength of the SUPERAID7 project: half of them as Gold Open Access and the remainder as Green Open Access.
    SUPERAID7 has been strongly represented, especially at SISPAD, IEDM and other conferences. In addition to two co-organized workshops associated with SISPAD 2016, the SUPERAID7 reporting period workshop foreseen in the Description of Action was organized in association with ESSDERC / ESSCIRC 2018. Finally, the CEA-Leti-NSP model has been proposed and discussions are ongoing for international standardization via the Compact Model Coalition.